1. Technical Field
Various embodiments relate to a semiconductor apparatus, and more particularly, to a delay locked loop circuit included in the semiconductor apparatus.
2. Related Art
Generally, a semiconductor apparatus such as a memory performs data communication with an external host apparatus such as a processor or a controller. The memory and host apparatus communicate data to each other synchronized with a system clock signal. The host apparatus is synchronized with the system clock signal and provides data to the memory and the memory is also synchronized with the system clock signal and provides data to the host apparatus. However, the system clock signal is apt to delay in the memory because there are a lot of logic circuits in the memory. Errors may occur during the data communication when data is output from the memory that is synchronized with the delayed system clock signal.
The memory in general includes a delay locked loop circuit in order to compensate a phase delay of the system clock signal. The delay locked loop circuit allows data to be synchronized with the system clock signal and output from the memory to the host apparatus by simulating an amount of delay of the system clock signal caused by internal circuits of the memory; and generating an internal clock signal where the delay of the system clock signal is compensated. The delay locked loop circuit includes a phase determination circuit configured to compare phases of the system clock signal and a feedback clock signal that is delayed by the simulated amount of delay. The delay locked loop circuit generates the internal clock signal based on the result of phase determination.
In a conventional phase determination circuit, anyone of a rising time point and a falling time point of anyone of a reference clock signal and a feedback clock signal is apt to change when power noise flows therein; or when a jitter of the reference clock signal or the feedback clock signal FBCLK occurs. Under such a circumstance, the conventional phase determination circuit may generate a phase determination signal of a high level by comparing an edge of a clock signal whose phase is changed due to the power noise or the jitter; and therefore the delay locked loop circuit may be locked incorrectly.